Anthropic Performance Take-Home

A performance optimization challenge for a custom VLIW SIMD architecture simulator, originally used by Anthropic for technical interviews.

Overview

This challenge involves optimizing a kernel that traverses binary trees while performing hash operations. The goal is to minimize execution cycles on a simulated VLIW SIMD processor.

Architecture Specifications

The challenge uses a custom VLIW SIMD architecture with five execution engines:

Key Parameters:

• SCRATCH_SIZE: 1536 32-bit words (register file)
• Vector Length (VLEN): 8 elements per vector operation
• Batch Size: 256 items processed per round
• Rounds: 16 iterations total

Performance Benchmarks

The Problem

Each round processes a batch of 256 items through these steps:

1. Load index and value from memory
2. XOR value with tree node value at index
3. Apply 6-stage hash function
4. Branch left (idx*2+1) if hash is even, else right (idx*2+2)
5. Wrap to root if past tree bounds
6. Store updated index and value

Optimization Strategies Applied

The optimization journey from 147K to ~1.4K cycles involves:

1. Vectorization (8x) - Process 8 batch items simultaneously using VALU
2. Instruction Packing (up to 23x) - Fill all engine slots per cycle
3. Loops - Replace unrolled code with cond_jump loops
4. Memory Batching - Use vload/vstore for 8-element transfers
5. Constant Caching - Pre-load constants to scratch space
6. Hash Pipelining - Overlap hash stages across elements

Combined theoretical speedup: 100x+ (8x vectorization * ~13x packing efficiency)

Background Knowledge

For the foundational concepts needed to understand this challenge, see the VLIW SIMD Architecture Notes:

• Scalar vs Vector - Understanding data parallelism
• ALU and Engines - Execution units
• VLIW Architecture - Instruction bundling
• Instruction Set - Available operations
• Optimization Strategies - General techniques

Key Commands

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# Run submission tests (official validation)
python tests/submission_tests.py

# Run cycle count test
python perf_takehome.py Tests.test_kernel_cycles

# Generate and view trace
python perf_takehome.py Tests.test_kernel_trace
python watch_trace.py  # Open browser, click "Open Perfetto"

# Validate tests unchanged (important!)
git diff origin/main tests/

Lessons Learned

1. VLIW forces explicit parallelism - You must manually schedule what runs together
2. Data dependencies are the bottleneck - Finding independent operations is key
3. Vectorization is powerful but constrained - Requires contiguous memory access patterns
4. Instruction packing requires careful planning - Scratch space allocation matters